Basically, the central processing unit (CPU) of a computer system is not directly powered by a power supply. Because the amplitude of the core voltage (Vcore) required by the CPU is varied with the actual load of the CPU and the amplitude of the core voltage (Vcore) may vary sharply according to the extremely heavy load or the extremely light load on the CPU, a voltage regulator module (VRM), specifically for providing powers to CPU, is commonly introduced on a motherboard.
FIG. 1 is a block diagram depicting a conventional single-phase VRM embedded on a motherboard (not shown). The single-phase VRM comprises a pulse-width-modulation (PWM) controller 10, a driver 20, and a power stage circuit 30, where a PWM signal is outputted from the PWM controller 10 to the driver 20.
Moreover, the driver 20 comprises a steering logic circuit 22 and two driving circuits (24, 26). According to the PWM signal, a first signal and a second signal are outputted from the steering logic circuit 22 to the driving circuits 24 and 26, respectively. According to the first signal and the second signal, a first driving signal (S1) and a second driving signal (S2) are outputted from the driving circuits 24 and 26, respectively.
Moreover, the power stage circuit 30 comprises an upper power field-effect-transistor (FET) (M1), a lower power FET (M2), an output choke (L), a resistor (Rs), and an output capacitor (Co). The drain of the upper power FET (M1) is connected to a voltage-power source (Vcc); the gate of the upper power FET (M1) is for receiving the first driving signal (S1); the source of the upper power FET (M1) is connected to a first end of the output choke (L). The drain of the lower power FET (M2) is connected to the first end of the output choke (L); the gate (G) of the lower power FET (M2) is for receiving the second driving signal (S2); the source of the lower power FET (M2) is connected to ground. The resistor (Rs) is coupled between a second end of the output choke (L) and a Vcore-output end that is for outputting the core voltage (Vcore). The output capacitor (Co) is coupled between the Vcore-output end and ground. Moreover, the Vcore-output end is connected to a power layer of the motherboard (not shown), and the power layer is further connected to the CPU and for providing the core voltage (Vcore) to the CPU. The upper power FET (M1) and the lower power FET (M2) are n-MOSFETs. The voltage-power source (Vcc) is 12V.
Via the driving of the first driving signal (S1) and the second driving signal (S2) respectively on the upper power FET (M1) and the lower power FET (M2), an output current (Io), sourced from the voltage-power source (Vcc), is generated and outputted to the Vcore-output end sequentially via the output choke (L) and the resistor (Rs). Because the output current (Io) is proportional to the load of the CPU, the load of the CPU can be determined via detecting the sense voltage (Vs) which is across the resistor (Rs), so as the single-phase VRM can dynamically provide powers based on the load of the CPU. That is, if the CPU is operated at a relative-heavy load, the output current (Io) is accordingly relative large, so as the sense voltage (Vs) is relative large. The relative large sense voltage (Vs) is then outputted to a feedback logic circuit 12 arranged in the PWM controller 10. Then, a PWM signal with a relative large pulse width, for informing the driver 20 and the power stage circuit 30 to generate a relative large output current (Io), is outputted from the PWM controller 10. On the other hand, if the CPU is operated at a relative-light load, the output current (Io) is accordingly relative small, so as the sense voltage (Vs) is relative small. The relative small sense voltage (Vs) is then outputted to the feedback logic circuit 12. Then, a PWM signal with a relative small pulse width, for informing the driver 20 and the power stage circuit 30 to generate a relative small output current (Io), is outputted from the PWM controller 10.
However, even the pulse width of the PWM signal can be dynamically modulated according to the real-time load of the CPU, a frequency for outputting the PWM signal is still a constant; where the frequency for outputting the PWM signal is named switching frequency (FSW). Please refer to FIG. 1 again. The PWM controller 10 further comprises an oscillator 11 connected to an external resistor (R1). The switching frequency (FSW) is generated by the oscillator 11 adopted with the external resistor (R1), and basically the switching frequency (FSW) is inverse proportional to the external resistance of the resistor (R1).
The phase in a VRM means the power stage circuit constituted by the FET, the choke, and the capacitor. In other words, a single-phase VRM means a VRM comprising one power stage circuit and a multi-phase VRM means a VRM comprising more than one power stage circuits. Because the modern CPU consumes more and more power, the multi-phase VRM, capable of providing a larger and more stable core voltage (Vcore), is commonly used on the modern motherboard.
FIG. 2 is a block diagram depicting a conventional four-phase VRM. The four-phase VRM comprises a PWM controller 40 and four current providing paths (41, 42, 43, 44). The current providing path 41 is constituted by a driver 50 and a power stage circuit 90; the current providing path 42 is constituted by a driver 60 and a power stage circuit 100; the current providing path 43 is constituted by a driver 70 and a power stage circuit 110; and the current providing path 44 is constituted by a driver 80 and a power stage circuit 120. Furthermore, four PWM signals (PWM1˜PWM4) are outputted from the PWM controller 40 to the four drivers (50, 60, 70, 80), respectively.
As described above, the four phases in the VRM depicted in FIG. 2 are constituted by the four drivers (50, 60, 70, 80) respectively adopted with the four power stage circuits (90, 100, 110, 120). Because each power stage circuit (90, 100, 110, 120) comprises a Vcore-output end and each Vcore-output end can output the core voltage (Vcore), the current power required by the CPU is a sum of the four output currents (Io1, Io2, Io3, Io4) respectively outputted from the current providing paths (41, 42, 43, 44). Because the function of the four drivers (50, 60, 70, 80) is exactly same as that of the driver 20 (FIG. 1) and the function of the four power stage circuits (90, 100, 110, 120) is exactly same as that of the power stage circuit 30 (FIG. 1), no unnecessary details are given here. Furthermore, because the oscillator 45 is connected to an external resistor (R1) having a constant resistance, the switching frequency (FSW) for outputting the four PWM signals (PWM1˜PWM4) is accordingly a constant.
With the increasing number of phases in the multi-phase VRM, the reliability and the stability of the operating frequency of the CPU are accordingly secured. However, comprising more phases in a multi-phase VRM also brings more unnecessary power waste due to the impedance factor resulted in the multi-phase VRM itself. Besides, compared to a multi-phase VRM comprising a relative small number of phases, the efficiency of a multi-phase VRM comprising a relative large number of phases is relative low if the multi-phase VRM is operated at a relative-light load.
FIG. 3A is a scheme illustrating efficiency curves derived from a conventional multi-phase VRM operated at two different configurations. As depicted in FIG. 3A, the efficiency of the multi-phase VRM operated at a configuration of 8 active phases is better than operated at a configuration of 4 active phases if the CPU is operated at a heavy load (CPU current greater than I_CPUref), where the I_CPUref is an intensity of a predefined reference CPU current. However, the efficiency of the multi-phase VRM operated at a configuration of 8 active phases is poor than operated at a configuration of 4 active phases if the CPU is operated at a light load (CPU current less than I_CPUref). Therefore, via dynamically modulating the configurations of the multi-phase VRM based on the load of the CPU, an optimal efficiency of the multi-phase VRM is obtained. That is, all the phases in the multi-phase VRM are active to provide powers to the CPU if the CPU is determined to operate at a heavy load, or, only a partial phases in the multi-phase VRM are active to provide powers to the CPU if the CPU is determined to operate at a light load.
FIG. 3B is a scheme illustrating an optimum efficiency curve derived from a conventional multi-phase VRM capable of operating at different configurations (only switched between configurations of 4 active phases and 8 active phases is took as an example). As depicted in FIG. 3B, the optimum efficiency curve (bold line) of the conventional multi-phase VRM is obtained if the all the eight phases are active to provide powers when the CPU is determined to operate at a heavy load (CPU current greater than I_CPUref) but only four phases are active to provide powers when the CPU is determined to operate at a light load (CPU current less than I_CPUref).
FIG. 4 is a flowchart of a control method of the conventional multi-phase VRM capable of operating at different configurations (only a switch between two configurations of 4 active phases and 8 active phases is took as an example). First, the multi-phase VRM is initialized to a configuration of 8 active phases (step 41). According to the initial configuration at step 41, the multi-phase VRM provides powers to CPU (step 43). The multi-phase VRM determines whether the CPU current is less than the I_CPUref or not (step 45). The number of the active phases in the multi-phase VRM is maintained at eight (step 49) if the CPU current is not less than I_CPUref, and then the multi-phase VRM provides powers to CPU (step 43) based on the configuration of 8 active phases. Alternatively, the number of the active phases in the multi-phase VRM is modulated to four (step 47) if the CPU current is less than I_CPUref, and then the multi-phase VRM provides powers to CPU (step 43) based on the configuration of 4 active phases.
However, the above-mentioned multi-phase VRM still can be improved to obtain the optimum efficiency.